Development of Advanced Encryption Standard Architecture with Sbox Parity
Keywords:AES, DES, shift row, mix column, FIFO
In this paper, an efficient AES (Advanced Encryption Standard) has been designed so that security levels can be increased which is caused due to faults and errors. The AES algorithm includes mainly 4 transformations, which are Sub-byte, Shift row, Mix column, Add round key. The security of Sbox has been increased by using even parity, which is used to detect faults rather than correction. A FIFO (First-In First-Out) is also considered to store the parity bits of Sbox. The expected parity bit of the output is predicted initially with the help of look up table (LUT) and compared with output parity bit. By this we can improve the fault coverage of Sbox. Since the Sbox parity architecture involves more MUX and XOR, their area is reduced by using the Binary Decision Diagram (BDD) approach and a pass transistor implementation of MUX which reduces the area drastically. Verilog HDL language is used to model the architecture and verification was done on Modelsim. Design, synthesized using a Cadence Register Transfer Level (RTL) complier tool. The synthesized result shows that there is an area overhead of 8 % and high fault coverage of 99.23 %.
National Institute of Standards and Technologies (NIST). Advanced encryption standard (AES). Fed. Inform. Process. Stand. 2000; 197, 1-51.
R Sever, AN Ismailglu, YC Tekmen, M Askar and B Okcan. A high sped FPGA implementation of the Rijndael algorithm. In: Proceedings of the Euromicro Symposium on Digital System Design, 2004, p. 358-62.
LIU Zhenzhen. Implementation of AES encryption based on FPGA. Mod. Electron. Tech. 2007; 23, 103-4.
N Sklavos and O Koufopavlou. Architectures and VLSI implementations of the AES-Proposal Rijndael. IEEE Trans. Comput. 2002; 51, 1454-9.
A Satoh, S Morioka, K Takano and S Munetoh. A compact Rijndael hardware architecture with SBox optimization. Lect. Notes Comput. Sci. 2000; 2248, 239-54.
MM Kermani and A Reyhani-Masoleh. Parity prediction of S-box for AES. In: Proceedings of the IEEE Canadian Conference on Electrical and Computer Engineering. Ottawa, Canada, 2006, p. 2357-60.
B Azam and B Ajmal. Reliability of nano-scaled logic gates based on binary decision diagrams. In: Proceedings of the International Conference on Modeling, Simulation and Visualization Methods. 2014, p. 1-5.
CH Hsu and BF Wu. Simple error detection methods for hardware implementation of advanced encryption standard. IEEE Trans. Comput. 2006; 55, 720-31.
V Ocheretnij, G Kouznetsov, R Karri and M Gossel. On-line error detection and BIST for the AES encryption algorithm with different SBox implementations. In: Proceedings of the 11th IEEE International On-Line Testing Symposium. Saint Raphael, French Riviera, France2005, p. 141-6.
G Bertoni, L Breveglieri, I Koren, P Maisti and V Piuri. Error analysis and detection procedures for a hardware implementation of the advance encryption standard. IEEE Trans. Comput. 2003; 52, 492-505.
GD Natale, ML Flottes and B Rouzeyre. A novel parity bit scheme for SBox in AES circuits. In: Proceedings of the Design and Diagnostics of Electronic Circuits and Systems. Kraków, Poland, 2007, p. 11-3.
P Maistri and R Leveugle. Double-data-rate computation as a countermeasure against fault analysis. IEEE Trans. Comput. 2008; 57, 1528-39.
A Satoh, T Sugawara, N Homma and T Aoki. High-performance concurrent error detection scheme for AES hardware. Lect. Notes Comput. Sci. 2008; 5154, 100-12.
M Mozaffari-Kermani, R Azarderakhsh, CY Lee and S Bayat-Sarmadi. Reliable concurrent error detection architectures for extended euclidean-based division over GF(2m). IEEE Trans. Very Large Scale Integrat. Syst. 2014; 22, 995-1003.
I Hussain and MA Gondal. An algorithm to generating inverse S-box for Rijndael Encryption standard. 3D Res. 2014; 5, 1-5.
How to Cite
Copyright (c) 2016 Walailak Journal of Science and Technology (WJST)
This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.